Conventional EEPROMs typically employ three to four transistors, which include a tunnel diode device coupled to the floating gate of the sense transistor to charge the latter and a select or row transistor to activate the cell. The use of three or four transistors to realize a cell substantially limits the size reduction possible for EEPROM arrays. Furthermore, typical EEPROM cells require the application of voltages in excess of 15 volts. This therefore requires special processing to reduce leakage and a larger layout to avoid unwanted field transistor turn-on, i.e., the use of high voltage transistors typically have longer channel lengths, and therefore, significantly larger sizes. This is especially the case with respect to the row transistor, since high voltage is applied to the source during the ERASE mode. The peripheral driving circuitry also requires higher voltage transistors to handle these high voltage driving signals.
In order to program select bits in the Flash EEPROM memory array, the separate select transistor is a required disadvantage to this separate transistor in that it increases the size of the memory array and does not allow for asymmetrical layout. Therefore, the separate select transistor does allow isolation of non-selected transistors within the same row as a selected cell. Further, whenever a select transistor is combined with a Fowler-Nordheim type EEPROM memory cell, a much higher voltage transistor is required for the select transistor, as compared to the cell itself and this requires a thicker layer of gate oxide. Additionally, the conventional technique has been to utilize a double poly process wherein the floating gates of the memory cells are fabricated in the first poly layer and the control gates of the memory cells are fabricated in the second poly layer, the second poly layer are also utilized to fabricate the row select transistors.